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VHDL

• VHDL: The POWER of FPGAs
  Posted by Ian on Wednesday 22/08/07

  Proponents know they can do a lot. But how much processing can we do with an FPGA and how does this compare with a DSP or fast CPU? This article attempts to find out......
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• VHDL: Simple ROM VHDL code example.
  Posted by Tom on Monday 04/06/07

  ROM is used to store predetermined values. This might be some boot code for a VHDL micro implementation, or maybe a set of tap weights for a FIR filter...
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• VHDL: Simple fixed point divider VHDL code example.
  Posted by Tom on Monday 04/06/07

  Here is a fixed point divider with remainder written in combinational logic...
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• VHDL: VHDL Data-path Optimisation; Race Conditions, Pipelining and Critical path overview.
  Posted by Tom on Wednesday 30/05/07

  There are a couple of data-path conditions in VHDL design that will cause the code to fail, race condition and the opposite propagation delay...
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• VHDL: How to cross Clock domains safely VHDL tutorial.
  Posted by Tom on Tuesday 29/05/07

  In this article we will explain the dangers of crossing clock domains and propose methods to do it safely.

  Crossing clock domains without precautions can cause problems due to timing issues;

  •Setup and Hold violations
  •Metastability conditions
  •Unreliable data ...
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• VHDL: Simple Debounce VHDL example code.
  Posted by Tom on Monday 28/05/07

  Any FPGA that has external signals via a pushbutton will suffer from contact bounce.

  Definition:
  Contact bounce (also called chatter) is a common problem with mechanical switches and relays...
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• VHDL: An overview of Clock Skew in Synchronous VHDL designs.
  Posted by Tom on Monday 28/05/07

  The golden rule in VHDL design is “All code will be synchronous.” Synchronous circuits are susceptible to a couple of problems one of which is clock skew.

  Clock skew (sometimes called timing skew) is a phenomenon in synchronous circuits in which the clock signal (sent from the clock circuit) arrives at different components at different times. This can be caused by many different things, such as...
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• VHDL: Designing Reliable VHDL Finite State Machines.
  Posted by Tom on Friday 25/05/07

  In this article we discuss how to design a reliable Finite State Machine by following the below VHDL design rules.

  1. Use a two process Entity structure.
  2. Selection of encoding style.
  3. Ensure all signals used in the Process appear in the process list.
  4. Ensure all combinations of input/output signals are included in the code.
  5. Ensure all outputs of the FSM are registered.
  6. Ensure all input are synchronous...
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• VHDL: Simple SPI Master Slave VHDL example code.
  Posted by Tom on Sunday 20/05/07

  SPI is a simple interface with high data rates, we have had SPI running at 1 MHz over short distances. The only precaution we had to take was to run a ground with every signal wire...
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• VHDL: Simple SPI Master VHDL example code.
  Posted by Tom on Thursday 10/05/07

  SPI is a simple interface with high data rates we have had SPI running at 1 MHz over short distances...
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• VHDL: Simple FIR VHDL example code.
  Posted by Tom on Monday 09/04/07

  This is a simple 4 tap FIR. This is a dedicated filter. A general purpose filter will be worked on later...
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• VHDL: Simple MAC (multiply-accumulate) VHDL example code.
  Posted by Tom on Friday 30/03/07

  The role of a MAC is to add two numbers together and then add the result to the previously accumulated value, which is then restored in the registers for future accumulation...
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• VHDL: Nasty GHDL/GTKWave bug, (signal reg).
  Posted by Tom on Thursday 29/03/07

  Came across a nasty bug either in GHDL or GTKWave.

  In the below code, if reg is defined then GTKWave will give me the following error ...
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• VHDL: Simple FIFO, VHDL example code.
  Posted by Tom on Monday 19/03/07

  This is a working example of a simple FIFO complete with full and empty signals, over flow and under flow protection...
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• VHDL: Simple ALU VHDL example code.
  Posted by Tom on Friday 16/03/07

  This a working example of a simple Arithmetic Logic Unit implemented in VHDL.

  You can get a simple ALU from...
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• VHDL: Simple RAM block with Bidirectional data bus, VHDL example code.
  Posted by Tom on Thursday 15/03/07

  This is just a variation to the previously posted Simple RAM block example.

  You can get a simple VHDL RAM block with ...
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• VHDL: Simple RAM block, VHDL example code
  Posted by Tom on Thursday 22/02/07

  FPGA’s are useful in various number crunching applications. Being able to complete 32/64 bit multiplications every clock cycle you can process a lot of data quickly. The place to store the pre-processed and processed data is the RAM block...
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• VHDL: VHDL Simple Serial Tx/Rx, VHDL example code.
  Posted by Ian and Tom on Wednesday 21/02/07

  This is a complete VHDL serial solution with test bench and GTKWave signals. You can get it from...
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• VHDL: VHDL simple serial receiver code example.
  Posted by Tom on Wednesday 14/02/07

  One of the easiest ways to communicate with an FPGA is via a standard RS232 serial port. The IO pins from the FPGA are not likely to be RS232 compatible so you must use a voltage shifter ...
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• VHDL: Installing GHDL and Compiling VHDL with GHDL tutorial.
  Posted by Tom on Tuesday 13/02/07

  I’m stuck in the hills of Pakistan and don’t have 1000US$ to buy a license for Altera Quartus II tool chain. So what can I use to compile and debug some VHDL code? GHDL is a...
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